The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to methods of patterning a structure.
A back-end-of-line (BEOL) interconnect structure may be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing with each other and with the environment external to the chip. Self-aligned patterning processes used to form a BEOL interconnect structure involve mandrels as sacrificial features that establish a feature pitch. Spacers, which have a thickness that is less than a dimension permitted by the current ground rules for optical lithography, are formed adjacent to the vertical sidewalls of the mandrels. After selective removal of the mandrels, the spacers are used as an etch mask to etch an underlying hardmask to define mandrel lines over areas from which the mandrels are removed and non-mandrel lines over areas between the spacers. The pattern of mandrel and non-mandrel lines is transferred from the hardmask to an interlayer dielectric layer as trenches in which the wires of the BEOL interconnect structure are formed.
Cuts may be formed in mandrels with a cut mask and etching in order to section the mandrels before the spacers are formed and to define gaps in the cut mandrels. Non-mandrel cuts may also be formed in the hardmask itself and define gaps that are filled by dielectric material when the spacers are formed. The gaps may be subsequently used to produce wires in the patterned interlayer dielectric layer that are spaced apart at their tips with a tip-to-tip spacing.
Improved methods of patterning a structure, such as a BEOL interconnect structure, are needed.